Mainframe server devices such as the zSeries® eServer®, available from assignee International Business Machines, Inc., use protocols for distributing and synchronising time among the client and server computers, for instance, to provide for system integrity in computer systems. In the past, the Time-Of-Day (TOD) clocks in the timing network were synchronized by means of an external box, the 9037 sysplex timer. Each Central Processing Complex (CPC) in the 9037 timing network stepped its TOD clock to the signals from the 9037. Briefly, a CPC refers to a system that may include one or more central processing units (CPUs) and associated hardware units such as main and expanded storage, TOD clocks, and channels that can be configured to operate under the control of an operating system. The stepping signals broadcast by the 9037 required special point-to-point links (called External Time Reference (ETR) links) from the 9037 to each CPC. A representative system implementing ETR offset values for synchronizing logical partitions of a logically partitioned machine is described in commonly-owned U.S. Pat. No. 6,209,106.
The Server Time Protocol (STP), which may replace the ETR as a time protocol in main server devices such as the zSeries®, implements a timing solution that does not include a common stepping signal. Timing information is communicated by means of messages with time stamps and other timing information, and each CPC must keep its TOD clock in step with the rest of the other CPCs by computing offsets and taking action to adjust the TOD clock. This is similar to the action performed by NTP (Network Timing Protocol), the difference being that NTP is normally implemented in a software layer where time stamps can be generated by the control program. The eServer zSeries® architecture has very stringent requirements on the TOD clock; it can be viewed by any problem program, all timestamps must be different, timestamps must never appear to step backwards, and timestamps must appear to be increasing, even when viewed by programs running on different CPUs in the CPC. To make the adjustments to the TOD clock required by the new timing solution, the stepping rate of the TOD clock must be speeded up or slowed down by very fine adjustments, and these adjustments must by observed simultaneously by all CPUs in the CPC.
The ETR architecture provides a means of synchronizing TOD clocks in different CPCs with a centralized time reference, which in turn may be set accurately on the basis of an international time standard. ETR time can be synchronized to international time by connecting an ETR unit (for example, the 9037) to an external time source (ETS). The Server Time Protocol (STP), however, has no easy way to obtain the same level of accuracy with respect to an international time standard that is achieved by the ETR. On the 9037-1, for example, the ETS was connected to the 9037 console by means of an RS 232 interface and the 9037 console was connected to the 9037-1 by means of a General Purpose Interface Bus (GPIB). This achieved an accuracy of about 5 milliseconds and was not considered acceptable to many customers. On the 9037-2 the ETS was connected directly to the 9037-2 by means of an RS-232 interface and an accuracy of about 1 millisecond was achieved. With the 9037-2, a pulse-per-second (PPS) coaxial connector was also added. When the PPS connection is used in conjunction with the RS-232, the 9037-2 can be synchronized to within about 100 microseconds of the PPS signal.
FIG. 1 shows a known high-availability ETR network with ETS and PPS. To provide for high availability, most ETR timing networks are designed to have no single point of failure. FIG. 1 shows two ETR units 102, 104 each connected to several servers 106, 108, each called a Central Processing Complex (CPC). The output from each ETR 102, 104 referred to as ETR signal is connected to an ETR attachment facility (EAF) port 110, 112, 114, 116 on each CPC 106, 108. To avoid any single point of failure, a high-availability ETR network 100 has two ETRs 102, 104 and each CPC has connections to both ETRs. Some ETR networks do not have all this redundancy. All CPCs, however, have two ETR ports, whether or not they are in a high availability network.
The external time source (ETS) unit 118, 120 obtains coordinated universal time (UTC) by means of dial-out, GPS, or other mechanism. The ETS unit 118 is connected to an ETR unit 102, for example, IBM 9037, by means of two connections RS-232 122, and optional pulse-per-second (PPS) 124. Similarly, the ETS unit 120 is connected to an ETR unit 104 by means of two connections RS-232 126, and optional pulse-per-second (PPS) 128. The RS-232 connection 122, 126 is used to communicate the time information and a special optional pulse-per-second connector 124, 128 is used to get a highly accurate timing pulse. Without the PPS signal, the accuracy is approximately +/−1.0 milliseconds. With the PPS signal, the accuracy is +/−100 microseconds. The ETR units 102, 104 communicate the timing information to each CPC 106, 108 by means of a special ETR interface referred to as the ETR signal. The accuracy of this interface is +/−2.0 microseconds.
FIG. 2 is a block diagram showing details of a known central processing complex (CPC). A CPC 200, for example, includes shared main storage 202, several CPUs 204, a Time of Day (TOD) clock 206, and an ETR attachment facility (EAF) with two ports 208, 210. The TOD clock 206 in each CPC is set to and synchronized to the ETR. The TOD clock may be stepped to either of the two ETRs, or from the local oscillator. The former case is called ETR stepping mode, the latter, local stepping mode.
FIG. 3 is a block diagram showing an ETR attachment facility (EAF) without PPS. It illustrates the EAF in detail for one EAF port. The TOD clock 302 is incremented by the TOD-clock-stepping signal. In the local stepping mode, this signal comes from a local oscillator 304. In the ETR stepping mode, the signal is derived from the ETR signal 306. The ETR signal 306 drives a phase-locked loop (PLL) 308, and a biphase converter 310 converts the ETR signal into a bit stream. At a module shown at 312, the bit stream is deserialized, symbols are recognized, and data is decoded to obtain the four different ETR data words 314 (DW1-DW4). One of the symbols decoded is the on-time-symbol. Recognition of the on-time symbol causes an on-time event (OTE). The OTE causes the contents of the first-level data register 314 to be gated into the second-level data register 316 and also causes the current contents of the TOD clock 302 to be gated into the time stamp register 318.
As described above, time information is communicated from the ETS by means of the RS-232 interface. In the 9037-1, the timing information is sent from the ETS to the 9037 console. In the 9037-2, the timing information is sent from the ETS directly to the 9037-2. With STP, the role of the 9037 console is performed by the Hardware Maintenance Console (HMC). There is no place to connect an RS-232 interface directly to the central processing complex (CPC), so the RS-232 connections must be made to the HMC in the same manner as with the 9037-1. The only interface available from the HMC to the CPC is the service interface. The service interface is designed to be flexible but not fast. It is used for all communication between human operators and the system and is also used by maintenance personnel to install changes to the Licensed Internal Code. This interface has a very high latency and variance. It is estimated, for example, that for HMC-initiated dial-out, an accuracy of about 100 milliseconds is the best that can be obtained, making the accuracy much worse than even the 9037-1.
An alternative solution is to replace the ETR Attachment Facility (EAF) in the CPC with a new interface card that would include RS-232 and PPS interfaces for input and a new protocol to the CPU to access this information. This solution would involve a substantial effort to define and implement such a new interface. Another option that may be considered is to provide a new stand-alone unit that would include RS-232 and PPS interfaces for input and the current ETR signals as output. This approach would require no change to the CPC as the current EAF would remain unchanged. However, design, implementation and manufacturing of such a unit would take a significant effort. Further, the price of a stand-alone unit would represent a significant increase in cost to a customer. Yet another choice is to use a standard input/output (I/O) communication path directly from the CPC to access timing information via Network Time Protocol (NTP) or other timing mechanisms. Like the other options, however, this would also require a significant design effort as there are no I/O paths available to the native machine.
It would thus be desirable to provide a system and method for achieving time of day accuracy in STP preferably without substantial design and implementation efforts.